Digital Design & Computer Architecture D3: Problem-Solving Session 3 (Spring 2026)

Digital Design & Computer Architecture D3: Problem-Solving Session 3 (Spring 2026)

by Onur Mutlu Lectures

Formal & Physical Sciences Computing & Cybersecurity UYComputer scienceUYFComputer architecture and logic design
🎙 Onur Mutlu Lectures 👥 64K 📅 March 16, 2026 ⏱ 40 min 👁 1K 📄 tutorial 🧭 2026-08-15
Available in: English (current) Français

Keywords

VerilogHDLFSMblocking assignmentnon-blocking assignment

Summary

This problem-solving session, led by a teaching assistant for Prof. Onur Mutlu’s Digital Design and Computer Architecture course at ETH Zürich, focuses on Verilog, a hardware description language. The session begins with an introduction to Verilog fundamentals, emphasizing that it is not a programming language but a means to describe hardware structures. The instructor explains key design principles such as hierarchical design and the importance of modularity. The main part of the session involves a live coding example of an odd counter (counting 1, 3, 5, 7, 9, 11) implemented as a finite state machine. The instructor demonstrates how to define inputs (clock, reset) and outputs (count), use always blocks, and distinguish between blocking and non-blocking assignments. He also addresses a common pitfall: assigning to the same variable in multiple always blocks, which can lead to ambiguous behavior. The session concludes with a past exam exercise where participants must fill in blanks in a Verilog module, testing their understanding of output declarations, register types, case statements, and proper assignment syntax. The instructor clarifies blocking vs. non-blocking assignments again in response to a question, explaining their use in combinational vs. sequential logic.

191 words

Critical Evaluation

Value of the Information & Strength of the Argument

The session provides valuable practical guidance on Verilog coding, which is essential for students in digital design. The instructor clearly explains the difference between blocking and non-blocking assignments, a common source of confusion, and illustrates it with examples. The argumentation is solid, as he justifies design choices (e.g., using a single always block for assignments to avoid ambiguity) and addresses potential pitfalls. The live coding example is effective in demonstrating the concepts, and the exam exercise reinforces learning. The session is well-structured and logically progresses from basics to more complex topics.

Scientific Rigor, Source Quality, Title Accuracy

The session is scientifically rigorous, as it is part of a university course and taught by a teaching assistant under the supervision of Prof. Onur Mutlu, a renowned researcher in computer architecture. The content aligns with standard Verilog practices and is consistent with academic teaching. The description provides links to relevant academic papers (e.g., on RowHammer, processing-in-memory) and course materials, which enhance the credibility of the content. The title accurately reflects the content, as it is indeed a problem-solving session for the course. The session does not rely on external sources during the video but references the course materials and recommended readings in the description.

211 words

Title / Content Match

The title accurately reflects the content: a problem-solving session for the Digital Design and Computer Architecture course, focusing on Verilog and hardware design.

Quality & Reliability

8/10

The session is an instructional tutorial by a recognized academic (Prof. Onur Mutlu) and his teaching team, focusing on Verilog coding practices. The content is technically accurate, well-structured, and includes practical examples and exam exercises. The video is part of a university course, and the description provides links to relevant academic papers and resources, enhancing credibility.

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Cited Sources

Concurring Sources

External References

Contribution & Novelties

The session provides a practical, hands-on approach to learning Verilog, which is often missing in theoretical lectures. It clarifies common misconceptions, such as the difference between blocking and non-blocking assignments, and emphasizes the importance of thinking in terms of hardware modules. The live coding example and exam exercise offer immediate application of concepts, making it a valuable resource for students.

Pour aller plus loin :

104 words

Radar Profile

The radar chart shows a balanced profile with high scores in quality of information and reliability, reflecting the academic rigor of the content. The quantity of information is moderate, as the session is focused and concise, while the technical level is appropriate for an introductory course. Overall, the session is a solid educational resource.

Reliability 8/10

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