Digital Design & Comp. Arch: L5: Hardware Description Languages and Verilog (Spring 2026)

Item: Digital Design & Comp. Arch: L5: Hardware Description Languages and Verilog (Spring 2026)
Rating: 5
Author: PostSingularity Institute

by Onur Mutlu

Formal & Physical Sciences Computing & Cybersecurity UYComputer science UYFComputer architecture and logic design

🎙 Onur Mutlu 👥 64K 📅 March 6, 2026 ⏱ 110 min 👁 3K 📄 lecture 🧭 2026-08-15

Available in: English (current) Français

Keywords

VerilogHDLstructural modelingbehavioral modelingfinite state machine

Summary

This lecture, part of the Digital Design and Computer Architecture course at ETH Zürich, introduces hardware description languages (HDLs) with a focus on Verilog. Professor Onur Mutlu explains the need for specialized languages to handle the complexity of modern microprocessors, which contain billions of transistors. He covers the two main design methodologies: top-down and bottom-up, emphasizing the importance of hierarchical design. The lecture then delves into Verilog syntax, including module definitions, ports, buses, bit slicing, and concatenation. Two primary modeling styles are presented: structural (gate-level) and behavioral (high-level functional description). The lecture includes examples of combinational logic implementation and hints at sequential logic and finite state machines, which are crucial for the upcoming labs where students will design a microprocessor. The recommended readings and slides are provided for further study.

130 words

Critical Evaluation

Value of the Information & Strength of the Argument

The lecture provides a solid foundation in HDLs, essential for digital design. It argues convincingly for the use of specialized hardware description languages over general-purpose programming languages, citing the inherent parallelism and specific constructs needed for hardware. The explanation of top-down and bottom-up design methodologies is clear and practical, with real-world analogies to software engineering. The argumentation is well-structured, building from the complexity problem to the solution offered by HDLs, and then to specific Verilog constructs. The lecture effectively motivates the topic by linking it to the design of a full microprocessor in subsequent lectures.

104 words

Title / Content Match

The title accurately reflects the content, which focuses on hardware description languages and Verilog.

Quality & Reliability

9/10

Lecture by a renowned professor in computer architecture, based on established course materials and recommended readings from reputable sources (arXiv, IEEE, ETH).

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Cited Sources

A Modern Primer on Processing in Memory — Recommended reading for understanding memory-centric computing, related to the lecture's context on computer architecture.
Memory-Centric Computing: Solving Computing's Memory Problem — Recommended reading on memory-centric computing, relevant to the lecture's broader themes.
Memory-Centric Computing: Recent Advances in Processing-in-DRAM — Recommended reading on recent advances in processing-in-DRAM.
Intelligent Architectures for Intelligent Computing Systems — Recommended reading on intelligent architectures, related to the lecture's motivation.
RowHammer: A Retrospective — Recommended reading on RowHammer, a hardware security issue, relevant to the lecture's context.
Fundamentally Understanding and Solving RowHammer — Recommended reading on RowHammer, related to hardware reliability.
Accelerating Genome Analysis via Algorithm-Architecture Co-Design — Recommended reading on genome analysis acceleration, showing application of computer architecture.
From Molecules to Genomic Variations: Accelerating Genome Analysis via Intelligent Algorithms and Architectures — Recommended reading on intelligent genome analysis, related to the lecture's themes.

Concurring Sources

Digital Design and Computer Architecture — Course website providing slides and additional materials.
Lecture slides (PDF) — Slides used in the lecture.

External References

Contribution & Novelties

This lecture provides a clear and comprehensive introduction to HDLs and Verilog, emphasizing the importance of understanding the underlying hardware for effective design. It bridges the gap between abstract design and physical implementation, preparing students for hands-on labs. The lecture’s unique value lies in its pedagogical approach, connecting fundamental concepts to real-world complexity and future AI-driven design tools.

Pour aller plus loin :

Verilog - Wikipedia — Overview of Verilog language and its history.
Hardware description language - Wikipedia — General introduction to HDLs.
SystemVerilog - Wikipedia — Extension of Verilog with additional features.
FPGA - Wikipedia — Hardware platform commonly used with HDLs.

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Radar Profile

The radar profile shows high scores across all dimensions, indicating a well-rounded and reliable lecture. The strong scores in information quantity and quality reflect the depth and accuracy of the content, while the technical level is appropriate for the target audience. The overall reliability is high, consistent with the lecturer's expertise and the use of credible sources.

Reliability 9/10