Digital Design & Comp. Arch: L22: Memory Hierarchy and Caches (Spring 2026)

Digital Design & Comp. Arch: L22: Memory Hierarchy and Caches (Spring 2026)

🎙 Dr. Mohammad Sadrosadati and Prof. Onur Mutlu 👥 64K 📅 May 16, 2026 ⏱ 111 min 👁 1K 📄 lecture 🧭 2026-08-15
Available in: English (current) Français

Keywords

memory hierarchycacheDRAMSRAMPCM

Summary

This lecture, part of the Digital Design and Computer Architecture course at ETH Zürich, focuses on memory hierarchy and caches. The instructors, Dr. Mohammad Sadrosadati and Prof. Onur Mutlu, begin by reviewing fundamental memory concepts, including idealized memory characteristics and the trade-offs between different memory technologies. They compare SRAM and DRAM in detail, highlighting differences in speed, density, cost, and refresh requirements. The lecture then introduces emerging memory technologies such as Phase Change Memory (PCM), discussing their potential advantages and challenges. The second half of the lecture shifts to cache design, covering cache organization, associativity, replacement policies, and the impact of cache parameters on performance. The instructors emphasize the importance of understanding memory hierarchy for optimizing system performance and energy efficiency. They also provide pointers to further reading and advanced courses. The lecture is technical and assumes prior knowledge of digital design and basic computer architecture.

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Critical Evaluation

Value of the Information & Strength of the Argument

The lecture provides a comprehensive and up-to-date overview of memory technologies and cache design, grounded in the instructors’ extensive research experience. The argumentation is solid, with clear explanations of trade-offs and references to relevant papers. The discussion of emerging memories like PCM and the challenges of DRAM scaling adds valuable insights beyond standard textbook material. The instructors effectively argue for a holistic view of memory hierarchy, considering performance, energy, and reliability.

Scientific Rigor, Source Quality, Title Accuracy

The lecture demonstrates high scientific rigor, with references to peer-reviewed papers and technical reports from reputable sources. The instructors are well-known researchers in the field, and the content aligns with current research directions. The title accurately reflects the content, which is a detailed exploration of memory hierarchy and caches. The lecture is well-structured, with clear transitions between topics and appropriate depth for an advanced undergraduate course.

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Title / Content Match

The title accurately reflects the content, which covers memory hierarchy and cache design in a university lecture format.

Quality & Reliability

9/10

Lecture by established researchers in computer architecture, with references to peer-reviewed papers and technical reports. Content is technically accurate and well-structured, though not peer-reviewed itself.

Key Moments

Cited Sources

Concurring Sources

External References

Contribution & Novelties

The lecture provides a comprehensive and current overview of memory hierarchy and caches, incorporating recent research on emerging memory technologies and their implications for system design. It bridges fundamental concepts with advanced topics like processing-in-memory and RowHammer, offering a unique perspective from leading researchers. The discussion of PCM and other resistive memories highlights the trade-offs and future directions in memory design.

Pour aller plus loin :

116 words

Radar Profile

The radar profile shows high scores across all dimensions, indicating a lecture that is information-dense, technically rigorous, and highly reliable. The balance between quantity and quality of information is strong, with a slight emphasis on technical depth.

Reliability 9/10