Digital Design and Computer Arch. - L16a: Out-of-Order Execution (Spring 2026)

Item: Digital Design and Computer Arch. - L16a: Out-of-Order Execution (Spring 2026)
Rating: 5
Author: PostSingularity Institute

by Onur Mutlu

Formal & Physical Sciences Computing & Cybersecurity UYComputer science UYFComputer architecture and logic design

🎙 Onur Mutlu 👥 64K 📅 April 22, 2026 ⏱ 96 min 👁 1K 📄 lecture 🧭 2026-08-15

Available in: English (current) Français

Keywords

out-of-order executiondynamic schedulingregister renamingreservation stationsdata flow

Summary

This lecture, part of ETH Zürich’s Digital Design and Computer Architecture course, delves into out-of-order execution, a technique used in virtually all modern processors to improve performance by dynamically scheduling instructions. The instructor, Prof. Onur Mutlu, begins by reviewing the in-order pipeline with a reorder buffer, highlighting its limitations, particularly the stall caused by a long-latency instruction that blocks subsequent independent instructions. He then introduces the concept of out-of-order execution, also known as dynamic instruction scheduling, which moves non-ready instructions into buffers (reservation stations) so that independent instructions can proceed. The lecture explains how register renaming eliminates false dependencies (WAR and WAW) and enables a larger physical register space, using tags to communicate readiness. The instructor illustrates the data flow graph that emerges from this approach and discusses the challenges of handling memory operations, which have variable latency. He also mentions alternative techniques like compiler scheduling, value prediction, and fine-grained multithreading, but argues that out-of-order execution is the most effective for single-thread performance. The lecture sets the stage for future topics such as load/store handling and branch prediction.

178 words

Critical Evaluation

Value of the Information & Strength of the Argument

The lecture provides a thorough and well-structured explanation of out-of-order execution, building on previous concepts and clearly motivating the need for dynamic scheduling. The argumentation is solid, using concrete examples and analogies to illustrate the problems and solutions. The instructor effectively demonstrates how register renaming and reservation stations enable out-of-order dispatch while maintaining correct program semantics. The discussion of alternative approaches (compiler scheduling, value prediction, multithreading) and their limitations strengthens the case for out-of-order execution. The lecture also highlights the importance of handling memory operations, which is a critical aspect of modern processor design.

Scientific Rigor, Source Quality, Title Accuracy

The lecture is scientifically rigorous, based on well-established principles in computer architecture. The instructor references his own research and recommended readings, including papers on processing-in-memory and RowHammer, which are relevant to the broader context. The title accurately reflects the content, focusing on out-of-order execution. The lecture is part of a reputable university course, and the slides are provided for further study. No comments were provided for analysis.

176 words

Title / Content Match

The title accurately reflects the content, which focuses on out-of-order execution as part of a digital design and computer architecture course.

Quality & Reliability

9/10

Lecture by a leading academic in computer architecture, based on established principles and supported by references to seminal papers and course materials.

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Cited Sources

A Modern Primer on Processing in Memory — Recommended reading for memory-centric computing
Memory-Centric Computing: Solving Computing's Memory Problem — Recommended reading on memory-centric computing
Memory-Centric Computing: Recent Advances in Processing-in-DRAM — Recommended reading on processing-in-DRAM
Intelligent Architectures for Intelligent Computing Systems — Recommended reading on intelligent architectures
RowHammer: A Retrospective — Recommended reading on RowHammer
Fundamentally Understanding and Solving RowHammer — Recommended reading on RowHammer
Accelerating Genome Analysis via Algorithm-Architecture Co-Design — Recommended reading on genome analysis
From Molecules to Genomic Variations: Accelerating Genome Analysis via Intelligent Algorithms and Architectures — Recommended reading on genome analysis
Lecture 16a Slides (pdf) — Slides for this lecture
Lecture 16a Slides (pptx) — Slides for this lecture
Digital Design and Computer Architecture course page — Course website

Concurring Sources

Computer Architecture: A Quantitative Approach — Standard textbook covering out-of-order execution

External References

Contribution & Novelties

This lecture provides a comprehensive and accessible explanation of out-of-order execution, a cornerstone of modern processor design. It builds on previous concepts and clearly articulates the motivation, mechanisms, and trade-offs. The instructor’s use of analogies and examples makes the material engaging and understandable. The lecture also connects to broader research themes in memory-centric computing, highlighting the importance of memory in future architectures.

Pour aller plus loin :

Tomasulo’s algorithm — A classic hardware scheduling algorithm that inspired out-of-order execution.
Register renaming — Technique to eliminate false dependencies.
Re-order buffer — Hardware structure for in-order retirement.
Dataflow architecture — Concept of data-driven execution.

102 words

Radar Profile

The radar profile shows high scores across all dimensions, indicating a lecture that is rich in information, technically deep, and highly reliable. The balance between quantity and quality is excellent, making it a valuable resource for understanding out-of-order execution.

Reliability 9/10