Digital Design & Comp. Arch: L4: Sequential Logic Design & Finite State Machines (Spring 2026)

Digital Design & Comp. Arch: L4: Sequential Logic Design & Finite State Machines (Spring 2026)

by Onur Mutlu

Formal & Physical Sciences Computing & Cybersecurity UYComputer scienceUYFComputer architecture and logic design
🎙 Onur Mutlu 👥 64K 📅 February 28, 2026 ⏱ 116 min 👁 3K 📄 lecture 🧭 2026-08-15
Available in: English (current) Français

Keywords

sequential logicfinite state machinesclocksynchronousstate

Summary

This lecture, part of the Digital Design and Computer Architecture course at ETH Zürich, continues the discussion on sequential logic design. Professor Onur Mutlu begins by reviewing the gated D latch and memory arrays, then introduces the concept of state using a combination lock example. He explains the difference between asynchronous and synchronous systems, emphasizing the importance of a clock signal for synchronization. The lecture covers the basics of finite state machines (FSMs), including state diagrams and state transitions, and discusses how to design synchronous sequential circuits. The professor also touches on the trade-offs between synchronous and asynchronous design, and mentions that the clock cycle must accommodate the longest combinational delay. The lecture concludes with an introduction to labs and FPGAs, setting the stage for future topics like hardware description languages and timing analysis.

134 words

Critical Evaluation

Value of the Information & Strength of the Argument

The lecture provides a solid foundation in sequential logic and finite state machines, using clear examples and analogies. The combination lock example effectively illustrates the concept of state, and the traffic light example clarifies the role of the clock. The professor’s argumentation is logical and well-structured, building on previous material and preparing students for more advanced topics. The value lies in the clarity of explanation and the emphasis on practical design considerations, such as the need for synchronous design in complex systems.

91 words

Title / Content Match

The title accurately reflects the content: the lecture covers sequential logic design and finite state machines, as part of a digital design and computer architecture course.

Quality & Reliability

9/10

Lecture by a renowned professor at ETH Zürich, based on established textbooks and accompanied by slides and recommended readings. The content is technically accurate and well-structured, with clear explanations and examples.

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Cited Sources

Concurring Sources

External References

Contribution & Novelties

This lecture provides a clear and thorough introduction to sequential logic and finite state machines, building on previous material. The use of real-world examples like combination locks and traffic lights makes abstract concepts accessible. The professor emphasizes the importance of synchronous design and the role of the clock, preparing students for more advanced topics in computer architecture.

Pour aller plus loin :

94 words

Radar Profile

The radar profile shows high scores in quantity of information, quality of information, and technical level, indicating a comprehensive and detailed lecture. The global reliability is also high, reflecting the professor's expertise and the use of credible sources.

Reliability 9/10