Digital Design & Comp. Arch: L18: VLIW and Systolic Array Architectures (Spring 2026)

Digital Design & Comp. Arch: L18: VLIW and Systolic Array Architectures (Spring 2026)

🎙 Onur Mutlu 👥 64K 📅 April 25, 2026 ⏱ 109 min 👁 2K 📄 lecture 🧭 2026-08-15
Available in: English (current) Français

Keywords

VLIWsystolic arrayinstruction-level parallelismcompilerhardware-software co-design

Summary

This lecture, part of the Digital Design and Computer Architecture course at ETH Zürich, focuses on two advanced execution paradigms: Very Long Instruction Word (VLIW) and systolic array architectures. The instructor, Prof. Onur Mutlu, begins by contrasting VLIW with superscalar execution, highlighting that VLIW shifts the burden of dependency checking from hardware to the compiler. He explains the concept of packing independent instructions into bundles, the lockstep execution model, and the challenges posed by variable memory latency. The lecture then transitions to systolic arrays, describing their structure as arrays of processing elements that rhythmically compute and pass data, making them highly efficient for matrix operations and machine learning accelerators. Prof. Mutlu discusses the trade-offs, including the need for static scheduling and the difficulty of handling memory stalls. He also touches on historical context, such as the ELI-512 project and commercial VLIW machines, and mentions modern applications like Google’s TPU. The lecture concludes with a summary of key takeaways and pointers to further reading.

163 words

Critical Evaluation

Value of the Information & Strength of the Argument

The lecture provides a thorough and well-structured explanation of VLIW and systolic arrays, building on previous lectures on superscalar execution. The argumentation is solid, with clear reasoning about the trade-offs between hardware complexity and compiler responsibility. Prof. Mutlu effectively uses examples and contrasts to illustrate concepts, and he addresses potential pitfalls such as memory latency and lockstep execution. The discussion of historical and modern implementations adds practical context, and the recommended readings provide avenues for deeper exploration.

Scientific Rigor, Source Quality, Title Accuracy

The lecture is scientifically rigorous, drawing on established research and the instructor’s expertise. The sources cited in the description are relevant and credible, including seminal papers on VLIW and systolic arrays, as well as recent work on memory-centric computing. The title accurately reflects the content, and the lecture maintains a high level of technical accuracy. The inclusion of course materials and recommended readings enhances the credibility of the presentation.

161 words

Title / Content Match

The title accurately reflects the content, covering VLIW and systolic array architectures in depth.

Quality & Reliability

9/10

Lecture by a renowned professor in computer architecture, based on established research and textbook material, with references to seminal papers and course materials.

Key Moments

Cited Sources

Concurring Sources

External References

Contribution & Novelties

The lecture provides a comprehensive overview of VLIW and systolic array architectures, emphasizing the trade-offs between hardware complexity and compiler responsibility. It connects historical developments to modern applications, such as machine learning accelerators, and highlights the importance of co-design. The discussion of memory-centric computing and RowHammer adds depth, showing the broader context of architectural innovation.

Pour aller plus loin :

109 words

Radar Profile

The radar profile shows high scores across all dimensions, indicating a well-balanced and comprehensive lecture. The strong scores in quantity and quality of information reflect the depth and accuracy of the content, while the high technical level and reliability underscore its academic rigor.

Reliability 9/10