Digital Design & Comp. Arch: L15: Dataflow, Superscalar Execution & Branch Prediction (Spring 2026)

Digital Design & Comp. Arch: L15: Dataflow, Superscalar Execution & Branch Prediction (Spring 2026)

by Onur Mutlu

Formal & Physical Sciences Computing & Cybersecurity UYComputer scienceUYFComputer architecture and logic design
🎙 Onur Mutlu 👥 64K 📅 April 18, 2026 ⏱ 108 min 👁 1K 📄 lecture 🧭 2026-08-15
Available in: English (current) Français

Keywords

dataflowsuperscalarbranch predictionout-of-orderTomasulo

Summary

This lecture, part of the Digital Design and Computer Architecture course at ETH Zürich, continues the discussion on out-of-order execution, then introduces dataflow architectures and superscalar execution, and finally delves into branch prediction. The instructor, Prof. Onur Mutlu, begins by recapping key concepts from the previous lecture, such as register renaming, reservation stations, and the reorder buffer, emphasizing the benefits of out-of-order execution in tolerating latency and exploiting irregular parallelism. He discusses the trade-offs, including increased hardware complexity and potential impact on clock cycle time. The lecture then explores dataflow architectures, where the dataflow graph is exposed to the programmer, contrasting with the hidden dataflow in out-of-order machines. Superscalar execution is introduced as a means to increase instruction throughput by fetching and executing multiple instructions per cycle, with examples from modern processors like AMD Zen and Apple’s chips. The second part of the lecture focuses on branch prediction, a critical technique to mitigate control hazards in pipelined and superscalar processors. The instructor explains the importance of accurate branch prediction, introduces various prediction schemes (static, dynamic, two-level adaptive predictors), and discusses the trade-offs between accuracy, hardware cost, and complexity. The lecture concludes with a summary of key takeaways and pointers to recommended readings.

202 words

Critical Evaluation

Value of the Information & Strength of the Argument

The lecture provides high-value information, offering a comprehensive overview of advanced processor design techniques. The argumentation is solid, building on established concepts and progressively introducing more complex ideas. The instructor effectively motivates the need for out-of-order execution, dataflow, and branch prediction by highlighting performance bottlenecks and trade-offs. The use of concrete examples from real processors (e.g., AMD Zen, Apple) strengthens the practical relevance. The discussion on branch prediction is particularly well-structured, covering both fundamental and advanced techniques, and the instructor’s explanations are clear and logical.

Scientific Rigor, Source Quality, Title Accuracy

The lecture demonstrates high scientific rigor, with references to influential papers and course materials. The instructor cites classic works such as the Tomasulo algorithm and the microarchitecture of superscalar processors, and provides links to slides and recommended readings. The title accurately reflects the content, which is consistent and well-organized. The lecture is part of a reputable academic course, and the instructor is a recognized expert in the field, enhancing credibility. However, as a lecture, it is not peer-reviewed, and some details may be simplified for pedagogical purposes.

187 words

Title / Content Match

The title accurately reflects the content, covering dataflow, superscalar execution, and branch prediction as advertised.

Quality & Reliability

9/10

Lecture by a renowned professor in computer architecture, based on established academic material, with references to influential papers and course slides. The content is technically rigorous and well-structured, though it is a lecture rather than peer-reviewed research.

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Cited Sources

Concurring Sources

  • Tomasulo's algorithm — The lecture's discussion on out-of-order execution is based on Tomasulo's algorithm, which is a foundational concept.
  • Branch predictor — The lecture's branch prediction section aligns with standard techniques described in this reference.

External References

Contribution & Novelties

The lecture provides a comprehensive and up-to-date overview of advanced processor design techniques, integrating classical concepts with modern implementations. It bridges the gap between theoretical out-of-order execution and practical superscalar designs, and offers a detailed treatment of branch prediction, a critical component for high-performance computing. The instructor’s insights into the trade-offs and design considerations are valuable for students and practitioners.

Pour aller plus loin :

  • Tomasulo’s algorithm — Foundational for out-of-order execution, directly relevant to the lecture’s discussion.
  • Branch predictor — Overview of branch prediction techniques, complementing the lecture’s content.
  • Superscalar processor — General concept of superscalar execution, relevant to the lecture’s second part.
  • Dataflow architecture — Alternative computing paradigm, discussed in the lecture.

114 words

Radar Profile

The radar profile shows high scores across all dimensions, indicating a lecture that is information-dense, technically rigorous, and highly reliable. The balanced profile suggests that the content is both comprehensive and well-presented, making it an excellent educational resource.

Reliability 9/10