Hardware Trojans & Microarchitectural Side-Channel Attacks: Detection and Mitigation Via Hardware-Based Methodologies

Hardware Trojans & Microarchitectural Side-Channel Attacks: Detection and Mitigation Via Hardware-Based Methodologies

by Alessandro Palumbo

Applied Sciences & Engineering Computing & Cybersecurity URComputer securityURHComputer fraud and hacking
🎙 Alessandro Palumbo 👥 154 📅 May 4, 2026 ⏱ 41 min 👁 36 📄 expert opinion 🧭 2026-08-15
Available in: English (current) Français

Keywords

hardware trojanside-channel attackmicroarchitecturehardware security moduleFPGA tampering

Summary

In this seminar, Alessandro Palumbo discusses hardware Trojans and microarchitectural side-channel attacks, focusing on detection and mitigation via hardware-based methodologies. He begins by explaining the threat model, noting that hardware components are often assumed trusted but can be compromised during the design and fabrication process. He introduces hardware Trojans, which can alter functionality, reduce reliability, or leak information, and mentions the TrustHub repository as a catalog of such Trojans. He then presents a hardware security module that monitors the runtime behavior of a processor, using a configuration phase to define legitimate behavior and a query phase to detect deviations. This module is lightweight and can detect attacks with low false positive/negative rates. He also discusses an obfuscation technique that scrambles registers and adds garbage instructions to prevent software-triggered Trojan activation. Next, he covers microarchitectural side-channel attacks, including timing attacks, Spectre, and Rowhammer, explaining how speculative execution and cache behavior can leak information. He proposes a programmable hardware module that monitors opcode frequencies and thresholds to detect such attacks. He also explores using machine learning to identify key features for detection, both offline and in hardware, and mentions using the Gem5 simulator to extract performance counters. Finally, he discusses detecting FPGA bitstream tampering using machine learning on hardware and software features, and concludes with open research questions.

216 words

Critical Evaluation

Value of the Information & Strength of the Argument

The talk provides valuable insights into hardware security, presenting concrete methodologies for detecting and mitigating hardware Trojans and side-channel attacks. The speaker demonstrates a clear understanding of the subject, explaining complex concepts such as speculative execution and cache attacks in an accessible manner. The argumentation is solid, supported by examples and experimental results, though some claims could benefit from more detailed evidence. The proposed hardware-based countermeasures are well-motivated, addressing the limitations of software-only defenses. The use of machine learning for feature selection and detection is a forward-looking approach, though the speaker acknowledges the challenges of implementing such methods in real hardware. Overall, the talk offers a comprehensive overview of the field and contributes original ideas for hardware security.

Scientific Rigor, Source Quality, Title Accuracy

The talk demonstrates scientific rigor in its methodology, with the speaker referencing the TrustHub repository and presenting experimental results. However, specific sources are not cited in detail, and the talk lacks a formal literature review. The title accurately reflects the content, which is a seminar presentation of ongoing research. The speaker’s affiliation with IRISA/Inria adds credibility, but the lack of published references limits the ability to verify claims. The content is well-structured and technically sound, but the absence of external citations and peer-reviewed backing reduces the overall rigor.

221 words

Title / Content Match

The title accurately reflects the content, which covers hardware Trojans and microarchitectural side-channel attacks, along with hardware-based detection and mitigation.

Quality & Reliability

7/10

The talk presents original research and methodologies, but lacks detailed peer-reviewed references and quantitative comparisons with existing solutions. The speaker is an associate researcher at IRISA/Inria, lending credibility, but the presentation is a seminar overview rather than a formal study.

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Cited Sources

Concurring Sources

  • TrustHub — Repository of hardware Trojans mentioned in the talk.

Contribution & Novelties

The talk presents novel hardware-based methodologies for detecting and mitigating hardware Trojans and microarchitectural side-channel attacks. The speaker introduces a programmable hardware security module that monitors runtime behavior, and an obfuscation technique to prevent software-triggered Trojan activation. The use of machine learning for feature selection and detection is a forward-looking approach, though the speaker acknowledges the challenges of implementing such methods in real hardware. The talk also explores using the Gem5 simulator to extract performance counters for attack detection, which is an innovative approach.

Pour aller plus loin :

134 words

Radar Profile

The radar profile shows high scores in technical level and information quantity, reflecting the advanced nature of the content. The quality and reliability scores are moderate, indicating that while the information is valuable, it lacks extensive external validation. The overall balance suggests a technically rich but not fully peer-reviewed presentation.

Reliability 7/10

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