Multi-Die Verification

Multi-Die Verification

by Semiconductor Engineering

Applied Sciences & Engineering Engineering & Technology TJFElectronics engineeringTJFCElectronics: circuits and components
🎙 Semiconductor Engineering 👥 30K 📅 October 13, 2025 ⏱ 16 min 👁 2K 📄 expert opinion 🧭 2026-08-16
Available in: English (current) Français

Keywords

multi-dieverificationchipletstestbenchdistributed simulation

Summary

In this interview, Ed Sperling of Semiconductor Engineering talks with Paul Graykowski, director of product marketing at Cadence, about the challenges and solutions for verifying multi-die systems built with chiplets. Graykowski explains that while the industry has focused on physical integration, verification has been overlooked. He highlights the need to reuse existing testbenches and scale them to multi-die systems, especially when chiplets come from different vendors. The discussion covers a divide-and-conquer approach using distributed simulation, where each die runs on its own simulator and communicates via interfaces like UCIe. Key challenges include synchronizing simulations, managing performance, and testing interactions between dies. Graykowski emphasizes shifting verification earlier in the design flow to improve first-time silicon success. He describes how Cadence’s solution allows leveraging existing testbenches and tests, with only incremental changes needed. Performance is maintained by using transaction-based interface modeling rather than cycle-accurate synchronization. The approach can run on-premises or in the cloud, and customers have reported up to 3x speedups. The interview concludes that multi-die verification is becoming more mainstream as the technology evolves.

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Critical Evaluation

Value of the Information & Strength of the Argument

The video provides valuable insights into the emerging field of multi-die verification, a topic that is not widely covered. It clearly explains the challenges of scaling verification from single-die to multi-die systems, including issues with testbench reuse, vendor diversity, and performance. The argumentation is coherent and based on practical experience, with concrete examples and a proposed solution (distributed simulation). However, the discussion is at a high level and lacks technical depth, such as specific algorithms or protocols. The value lies in raising awareness and outlining a methodology rather than providing detailed technical guidance.

Scientific Rigor, Source Quality, Title Accuracy

The video is an expert interview, so the primary source is the interviewee’s expertise. No external sources are cited, and the description does not include links to further references. The title accurately reflects the content, which focuses on verification for multi-die systems. The discussion is consistent with known industry trends, but the lack of citations and the promotional nature of the content (being from a vendor) slightly reduce its scientific rigor. The information appears reliable based on the speaker’s credentials, but it is not independently verified.

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Title / Content Match

The title accurately reflects the content, which focuses on verification challenges and approaches for multi-die systems.

Quality & Reliability

7/10

The video features an expert from Cadence discussing multi-die verification challenges and solutions. It is based on industry experience and product knowledge, but lacks detailed technical depth and independent verification. The information is credible but promotional in nature.

Key Moments

Markers derived by PSI from the transcript: the creator did not define chapters.

Contribution & Novelties

The video provides an overview of multi-die verification, a relatively new challenge in semiconductor design. It introduces the concept of distributed simulation for verification, where each die runs on its own simulator and communicates via interfaces. This approach allows reuse of existing testbenches and tests, reducing the effort required for multi-die verification. The discussion highlights the importance of shifting verification earlier in the design flow to improve first-time silicon success. The video also mentions specific tools like Cadence’s Xcelium distributed simulation app, but does not provide detailed technical specifications.

Pour aller plus loin :

  • UCIe specification — Official website for the Universal Chiplet Interconnect Express standard, relevant to the interfaces discussed.
  • Chiplet design and verification — An article from Semiconductor Engineering on chiplet verification challenges, providing additional context.
  • Distributed simulation in EDA — Wikipedia article on distributed computing, which underpins the distributed simulation approach.

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Radar Profile

The radar profile shows moderate scores across all dimensions, indicating a balanced but not exceptional video. The highest scores are in quality of information and reliability, reflecting the expert interview format, while quantity of information and technical level are slightly lower, suggesting a high-level overview rather than deep technical detail.

Reliability 7/10

💬 No comments were provided for analysis.