From AI Power Challenges to Future Transistors and Crystal Structures | 2026 L2

Value of the Information & Strength of the Argument

The lecture provides valuable insights into the connection between AI-driven power demands and semiconductor innovation. It effectively argues that power efficiency, not just computing capability, is the primary bottleneck driving future transistor development. The presentation is well-structured, using concrete examples like GPU power consumption and power converter losses to illustrate complex concepts. The discussion of transistor evolution is logically sequenced, helping students understand the rationale behind each architectural change. The argumentation is solid, relying on established physics and recent industry trends, although it does not present novel research.

Scientific Rigor, Source Quality, Title Accuracy

The scientific rigor is high for an educational lecture: the content aligns with established semiconductor physics and current industry roadmaps. The lecturer references real developments such as TSMC’s technology forum and Intel’s roadmap, and mentions recent CFET demonstrations from 2024-2025. However, no external sources are explicitly cited in the transcript, and the lecture is more of a synthesis than an original contribution. The title accurately captures the scope, from AI power challenges to transistor evolution and crystal structures, with clear relevance to device physics. The adequacy between title and content is strong.

The title accurately reflects the content, covering AI power challenges, transistor evolution, and crystal structures.

8/10

Lecture from a university professor with consistent technical content, based on established semiconductor physics and industry roadmaps. No external sources cited within the transcript, but the material aligns with known literature and is appropriately structured for a graduate-level course.

Markers derived by PSI from the transcript: the creator did not define chapters.

• 00:00Course introduction and recap of subthreshold slope importance.
• 10:00AI power challenges: GPU power consumption and data center bottlenecks.
• 20:00Power conversion chain and the role of GaN and SiC power devices.
• 30:00Moore's Law and More-than-Moore: scaling vs. diversification.
• 40:00Transistor evolution: from planar to FinFET to GAA nanosheet.
• 50:00Advanced architectures: forksheet and CFET (complementary FET).
• 1:00:00Roadmaps from IMEC, TSMC, and Intel; backside power delivery.
• 1:10:00Future materials: 2D materials and carbon nanotubes.
• 1:20:00Semiconductor materials classification and PN junction fundamentals.
• 1:30:00Crystal structures, unit cells, Miller indices, and defects.

• 2024 IEDM paper on CFET demonstration — Mentioned in lecture as first silicon demonstration of CFET.
• 2025 paper on CFET ring oscillator — First demonstration of CFET ring oscillator.
• IMEC roadmap — Future transistor architecture until 2036.
• TSMC Technology Forum 2026 — Identified FinFET, nanosheet, and CFET.
• Intel roadmap — High-k metal gate, FinFET at 22nm, RibbonFET, backside power.